CCFS 2022 Speakers

Keynote Speaker: Russell Tessier is a Professor of Electrical and Computer Engineering at the University of Massachusetts Amherst. He has performed research in FPGAs and reconfigurable computing for over 30 years. He was a founder of Virtual Machine Works, a logic emulation company which is now owned by Siemens. Among many other service roles, he has served on the Program Committee of the ACM/SIGDA International Symposium on FPGAs since 2000. His recent research interests include FPGA security and cloud FPGA computing.

Talk Title: Hardware Security Solutions for Multi-Tenant FPGAs

Abstract: The increased use of FPGAs in cloud and embedded computing environments has led to a number of potential security risks. The sizable amount of logic resources in these devices makes them amenable to sharing across multiple untrusted tenants. However, the co-location of multiple independent circuits presents the possibility of side-channel and fault injection attacks. In this talk, a series of multi-tenant FPGA attack remediations will be described. These solutions have been performed on multiple families of Intel FPGAs, including state-of-the-art Stratix 10 devices. A sensor-based remediation approach that can prevent a voltage attack within 20 microseconds in a Stratix 10 device will be presented along with a fault remediation technique using partial FPGA reconfiguration. Finally, a recovery approach that allows for fault-free computation rollback for an RSA encryption circuit is described.

Talk Title: NNReArch: A Tensor Program Scheduling Framework Against Neural Network Architecture Reverse Engineering

Bio: Yukui Luo is a Ph.D. candidate at the Electrical and Computer Engineering Department of Northeastern University, advised by Prof. Xiaolin Xu. His research interests are FPGA virtualization, hardware security, and the security of acceleration IPs.

Abstract: Gaining knowledge of the association between the low-level tensor programs and the EM emanations, we propose NNReArch, a lightweight tensor program scheduling framework against side-channel-based DNN model architecture reverse engineering. Specifically, NNReArch targets reshaping the EM traces of different DNN operators by scheduling the tensor program execution of the DNN model so as to confuse the adversary. NNReArch is a comprehensive protection framework supporting two modes, a balanced mode that strikes a balance between the DNN model confidentiality and execution performance and a secure mode where the most secure setting is chosen. We implement and evaluate the proposed framework on the open-source VTA with state-of-the-art DNN architectures. The experimental results demonstrate that NNReArch can efficiently enhance the model architecture security with a small performance overhead. In addition, the proposed obfuscation technique makes reverse engineering the DNN architecture significantly harder.

Talk Title: Complete and Improved FPGA Implementation of Classic McEliece

Bio: I am a second-year Ph.D. student and a researcher at CASLAB from Yale University, advised by Prof. Jakub Szefer. My research is focused on efficient and secure implementations of crypto algorithms and quantum computer security. Before joining Yale, I worked as a Security Researcher at a research organization known as Technology Innovation Institute. In the past, I have been a researcher at the Cryptographic Engineering Research Group at George Mason University.

Talk Title: FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA

Bio: Shijin Duan is a second-year Ph.D. candidate at the Electrical and Computer Engineering Department of Northeastern University, advised by Prof. Xiaolin Xu. His interests are high-efficient computing, FPGA acceleration, and hardware computing.

Abstract: In this work, we propose FPGAPRO: a defense framework leveraging Placement, Routing, and Obfuscation to mitigate the secret leakage on FPGA components, including long-wires, medium-wires, and logic elements in CLB. As a user-friendly defense strategy, FPGAPRO focuses on protecting the security-sensitive instances meanwhile considering critical path delay for performance maintenance. As the proof-of-concept, the experimental result demonstrates that FPGAPRO can effectively reduce the crosstalk-caused side-channel leakage by 138 times. Besides, the performance analysis shows that this strategy prevents the maximum frequency from timing violation.

Talk Title: Don't Wait for SHAKE256: A Fast HQC Hardware Implementation

Bio: Chuanqi Xu is a third Ph.D. student at Yale University, advised by Prof. Jakub Szefer. His research interests lie in quantum computing and computer security. He is currently working on quantum computer security, where he designs attack and defense mechanisms on quantum computers and quantum cloud providers. He is also working on RTL design (Verilog) targeting FPGAs, where he implements Post-Quantum Cryptography (PQC) schemes that are secure under both classical and quantum computer attacks. He received his B.S. in applied physics from University of Science and Technology of China.