Lectures will be held on Mondays and Wednesdays from 9:00pm to 10:15am in the new Greenberg teaching center between Becton and Dunham, room C037.
This course introduces students to computer architecture and covers topics of computer organization, microprocessors, caches and memory hierarchies, I/O, and storage. The course gives an overview of microprocessor design ideas such as pipelining, out-of-order processors, branch prediction, instruction level parallelism, thread-level parallelism and cache coherency. Issues of performance, energy and security are raised, along with introduction to processor benchmarking. Select readings from current academic literature augment course textbook and lecture notes. Course also includes FPGA programming assignemnts and a final project which focuses on design, implementation, and evaluation of a processor architecture.
EENG 201, or with permission of instructor; C / C++ programming experience; Verilog / VHDL programming experience
Deadlines and work submission: All deadlines are posted in the schedule. Homeworks are due by 5pm EST unless otherwise stated. There is 25% penalty for each day late, penalty will not be prorated, e.g. 1 hour late is still 25% penalty. All work is to be submitted electroncially via Canvas drop box system and will be automatically downloaded at the due date and time.
Collaboration policy: Collaboration can be a great learning tool, so students are encouraged to study together and help each other out. However, unless otherwise stated, all work is individual. Do not copy other's homework or code. Violations of this policy will not be tolerated and referred to the Dean.
Attendance: You are responsible for all the material covered in class. The course covers materials that may not all be in the textbook or printed handouts, so attendance is crucial for good performance in the course. If you miss a class, please get a Dean's excuse and make an appointment with the instructor to go over the material that was in the missed lecture.
Academic Integrity: Please do not cheat or copy other's work. Make sure to cite any sources. All homeworks and submitted code will be reviewed for similarities.
Re-grading Policy: Please bring up any issues with re-grading homework or examination within one week from when the homework or examination is returned. Please write 2 ~ 3 sentences to justify each problem you would like re-graded and state why. Original homework or examination along with printed request should be given to instructor.
Portable Electronic Devices: Using portable electronic devices for nonacademic purposes during class time is distracting to your peers and the instructor. Please silence all such devices.
Special Accommodations: If you require any special accommodations please notify the instructor as soon as possible. This includes any religious practice which may interfere with completion of a scheduled examination, project or homework. Please contact instructor early on in the course to arrange a meeting where we can plan for any needed accommodations.
Academic integrity is a core institutional value at Yale. It means, among other things, truth in presentation, diligence and precision in citing works and ideas we have used, and acknowledging our collaborations with others. In view of our commitment to maintaining the highest standards of academic integrity, the Graduate School Code of Conduct specifically prohibits the following forms of behavior: cheating on examinations, problem sets and all other forms of assessment; falsification and/or fabrication of data; plagiarism, that is, the failure in a dissertation, essay or other written exercise to acknowledge ideas, research, or language taken from others; and multiple submission of the same work without obtaining explicit written permission from both instructors before the material is submitted. Students found guilty of violations of academic integrity are subject to one or more of the following penalties: written reprimand, probation, suspension (noted on a student's transcript) or dismissal (noted on a student's transcript).
Web page design copied from MIT's 6.888 Parallel and Heterogeneous Computer Architecture page; used with permission.