Shanquan Tian

• Hi, I am a PhD candidate in Computer Architecture and Security Lab (CASLAB) at Yale University, working with Professor Jakub Szefer. During my PhD study, I got my M.S. and M.Phil in 2019 and 2020. Before coming to Yale, I graduated from USTC with the Bachelor's degree in 2017.
  
  My research focuses on the computer architecture and cloud infrastructure security, including hardware security of machine learning accelerators, the novel architectures to accelerate different algorithms, and the security of FPGA-accelerated cloud environments.
  
  Please find my CV here.
  
     Email     Google Scholar       LinkedIn

Peer-reviewed Publications

• Ilias Giechaskiel, Shanquan Tian, and Jakub Szefer, "Cross-VM Information Leaks in FPGA-Accelerated Cloud Environments", in Proceedings of the International Symposium on Hardware Oriented Security and Trust (HOST), December 2021.
  [ BibTeX ]  [ PDF ] 

• Julia Burgiel, Daniel Esguerra, Ilias Giechaskiel, Shanquan Tian, and Jakub Szefer, "Characterization of IOBUF-based Ring Oscillators", in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2021.
  [ BibTeX ]  [ PDF ] 

• Shayan Moini, Shanquan Tian, Daniel Holcomb, Jakub Szefer, and Russell Tessier, "Power Side-Channel Attacks on BNN Accelerators in Remote FPGAs", in IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2021.
  [ BibTeX ]  [ arXiv version ] 

• Shanquan Tian, Shayan Moini, Adam Wolnikowski, Daniel Holcomb, Russell Tessier, and Jakub Szefer, "Remote Power Attacks on the Versatile Tensor Accelerator in Multi-Tenant FPGAs", in Proceedings of the International Symposium on Field-Programmable Custom Computing Machines (FCCM'21), May 2021.
  Best Paper Candidate
  [ BibTeX ] 

• Shanquan Tian, Ilias Giechaskiel, Wenjie Xiong, and Jakub Szefer, "Cloud FPGA Cartography using PCIe Contention", in Proceedings of the International Symposium on Field-Programmable Custom Computing Machines (FCCM'21), May 2021.
  [ BibTeX ] 

• Shayan Moini, Shanquan Tian, Jakub Szefer, Daniel Holcomb, and Russell Tessier, "Remote Power Side-Channel Attacks on BNN Accelerators in FPGAs", in Design, Automation and Test in Europe Conference (DATE'21), February 2021.
  [ PDF ]  [ BibTeX ]  [ arXiv version ] 

• Shanquan Tian, Andrew Krzywosz, Ilias Giechaskiel, and Jakub Szefer, "Cloud FPGA Security with RO-Based Primitives", in Proceedings of the International Conference on Field-Programmable Technology (FPT'20), December 2020.
  [ BibTeX ] 

• Wen Wang, Shanquan Tian, Bernhard Jungk, Nina Bindel, Patrick Longa, and Jakub Szefer, "Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA", in Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES'20), September 2020.
  [ PDF ]  [ BibTeX ]  [ ePrint version ]  [ CODE ] 

• Shanquan Tian, Wenjie Xiong, Ilias Giechaskiel, Kasper Rasmussen, and Jakub Szefer, "Fingerprinting Cloud FPGA Infrastructures", in Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA'20), February 2020.
  [ PDF ]  [ BibTeX ]  [ CODE ]

• Shanquan Tian, Wen Wang, and Jakub Szefer, "Merge-Exchange Sort Based Discrete Gaussian Sampler with Fixed Memory Access Pattern", in Proceedings of the International Conference on Field-Programmable Technology (FPT'19), December 2019.
  [ PDF ]  [ BibTeX ]  [ CODE ]

• Shanquan Tian, and Jakub Szefer, "Temporal Thermal Covert Channels in Cloud FPGAs", in Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA'19), February 2019.
  [ PDF ]  [ BibTeX ]  [ CODE ] 

Open-Source Code

• Most of my code is published on our lab website here  

• [ CODE ]  Cloud FPGA Security with RO-Based Primitives  

• [ CODE ]  Fingerprinting Cloud FPGA Infrastructures (using DRAM PUFs on AWS F1)  

• [ CODE ]  Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA  

• [ CODE ]  Merge-Exchange Sort Based Discrete Gaussian Sampler with Fixed Memory Access Pattern  

• [ CODE ]  Temporal Thermal Covert Channels in Cloud FPGAs  

Technical Reports

• Shayan Moini, Shanquan Tian, Jakub Szefer, Daniel Holcomb, and Russell Tessier, "Remote Power Side-Channel Attacks on CNN Accelerators in FPGAs", November 2020.
  [ arXiv ] 

Hardware Demos in Academic Conferences

• Shanquan Tian, Wenjie Xiong, Ilias Giechaskiel, Kasper Rasmussen, and Jakub Szefer, "Demo of Fingerprinting Cloud FPGAs", Hardware Demo at the International Symposium on Hardware Oriented Security and Trust (HOST'20), December 2020.