The tutorial will be given on May 6th, 2019 (Monday) from 3:30pm to 6:00pm.
The tutorial will be in the International Ballroom B, The Hilton, Tysons, VA, USA (as part of the HOST conference).
The objective of this tutorial is to present the principles that processor architects and designers should use to ensure their processor architectures are secure, especially given side-channel attack threats which have re-emerged as a significant threat to security since Spectre and Meltdown (and their variants) have been publicized over the last year. First, the tutorial will overview secure processor architectures, present design patterns that can be gleaned from the existing research works, and will derive the principles that inform design of the secure processor architectures. Second, the tutorial will present details of the various secure cache architectures which have been developed in academia (and industry), their resistance to various side-channels, and performance impact of each. Third, the tutorial will present details of Spectre and Meltdown attacks (and their various variants presented to date) and hardware defenses (and estimations of performance impact of each). This tutorial will thus cover the three main contemporary research areas of secure processor architectures: the architectures themselves, secure caches, and speculation and side-channel attacks.
The tutorial is partly based on a book recently published by Jakub Szefer. This tutorial will complement the book with new material, while the book gives a more in-depth discussion of the topics covered in the tutorial. It is available for purchase, or many universities provide free PDF version of the book through their electronic subscriptions.
The program of the tutorial is as follows:
15:30 – 16:10 Secure Processor Architectures
16:10 – 16:20 Break
16:20 – 17:10 Secure Processor Caches
17:10 – 17:20 Break
17:20 – 18:00 Transient Execution Attacks and Mitigations
18:00 Wrap Up
Tutorial slides are available here (10.3MB).