Research Projects

Cloud FPGA Security

This project investigates how to make cloud-based FPGAs and FPGA cyber-infrastructures secure. It focuses on evaluating and defending various types of side channels and covert channels, as well as how to enable secure multi-tenant Cloud FPGAs.

Recent publications:

Ilias Giechaskiel, Kasper Rasmussen, and Jakub Szefer, "Measuring Long Wire Leakage with Ring Oscillators in Cloud FPGAs", in Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL), September 2019.
[ BibTeX

Shanquan Tian and Jakub Szefer, "Temporal Thermal Covert Channels in Cloud FPGAs", in Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA), February 2019.
[ PDF ]  [ BibTeX ]  [ CODE coming Soon ] 

Secure Processor Architectures

This project investigates design of secure procesosr architectures, including defenses of side channels and covert channels.

Recent publications:

Shuwen Deng, Wenjie Xiong, and Jakub Szefer, "Secure TLBs", in Proceedings of the International Symposium on Computer Architecture (ISCA), June 2019.
[ BibTeX ]  [ CODE coming June 2019 ] 

Jakub Szefer, "Survey of Microarchitectural Side and Covert Channels, Attacks, and Defenses", in Journal of Hardware and Systems Security, September 2018.
[ PDF ]  [ BibTeX ]  [ prior ePrint


Hardware Security Verification

This project investigates developing a new hardware security verification methodology that hardware processor architects can deploy to check security properties of their architectures in a scalable and semi-automated manner at design time. The project combines hardware description tools and languages with model checkers and theorem provers to create the methodology.

Recent publications:

Shuwen Deng, Doğuhan Gümüşoğlu, Wenjie Xiong, Y. Serhan Gener, Onur Demir, and Jakub Szefer, "SecChisel Framework for Security Verification of Secure Processor 
Architectures", in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), June 2019.
[ BibTeX ]  [ prior ePrint

Shuwen Deng, Wenjie Xiong, and Jakub Szefer "Cache Timing Side-Channel Vulnerability Checking with Computation Tree Logic" in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), June 2018.
[ PDF ]

Onur Demir, Wenjie Xiong, Faisal Zaghloul, and Jakub Szefer, "Survey of Approaches for Security Verification of Hardware/Software Systems", August 2016.
[ ePrint ]

Physically Unclonable Functions

This project explores the design and implementation of novel Physically Unclonable Functions (PUFs). A PUF is a piece of hardware that has unique and stable physical characteristics, which emerges due to variations in the fabrication processes. The project focuses on leveraging the decay characteristics of modern DRAM chips in commodity off-the-shelf systems to design practical DRAM PUFs.

Recent publications:

Shuai Chen, Wenjie Xiong, Yehan Xu, Bing Li, and Jakub Szefer, "Thermal Covert Channels Leveraging Package-On-Package DRAM", in Proceedings of the International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom), August 2019.
[ BibTeX ]  [ CODE coming August 2019 ] 

Wenjie Xiong, André Schaller, Stefan Katzenbeisser, and Jakub Szefer, "Dynamic Physically Unclonable Functions", in Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), May 2019.
[ PDF ]  [ BibTeX

André Schaller, Wenjie Xiong, Nikolaos Athanasios Anagnostopoulos, Muhammad Umair Saleem, Sebastian Gabmeyer, Boris Škorić, Stefan Katzenbeisser, and Jakub Szefer, "Decay-Based DRAM PUFs in Commodity Devices", in IEEE Transactions On Dependable And Secure Computing, vol. 16, issue 3, May 2019.
[ PDF ]  [ BibTeX

Wenjie Xiong, Nikolaos Athanasios Anagnostopoulos, André Schaller, Stefan Katzenbeisser, and Jakub Szefer, "Spying on Temperature using DRAM", in Proceedings of the Design, Automation, and Test in Europe (DATE), March 2019.
[ PDF ]  [ BibTeX ]  [ CODE

André Schaller, Wenjie Xiong, Muhammad Umair Saleem, Nikolaos A. Anagnostopoulos, Stefan Katzenbeisser, and Jakub Szefer "Intrinsic Rowhammer PUFs: Leveraging the Rowhammer Effect for Improved Security" in Proceedings of the International Symposium on Hardware Oriented Security and Trust (HOST), May 2017.
[ PDF ] [ BibTeX ] [ CODE ]

Wenjie Xiong, André Schaller, Nikolaos A. Anagnostopoulos, Muhammad Umair Saleem, Sebastian Gabmeyer, Stefan Katzenbeisser, and Jakub Szefer, "Run-time Accessible DRAM PUFs in Commodity Devices" in Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES), August 2016.
[ PDF ] [ BibTeX ] [ CODE ]


Post-Quantum Cryptography

This project explores implementing new types of cryptographic algorithms and optimizing their area, performance and energy needs, as well as integrating them as accelerators into real cloud servers. Current focus of the project is on code-based cryptographic algorithms which are expected to be secure even against attacks that leverage quantum computers.

Recent publications:

Wen Wang, Bernhard Jungk, Julian Wälde, Shuwen Deng, Naina Gupta, Jakub Szefer, and Ruben Niederhagen, "XMSS and Embedded Systems: XMSS Hardware Accelerators for RISC-V", in Proceedings of the Selected Areas in Cryptography (SAC), August 2019.
[ BibTeX ]  [ prior ePrint ]  [ CODE

Wen Wang, Jakub Szefer, and Ruben Niederhagen, "Post-Quantum Cryptography on FPGAs: the Niederreiter Cryptosystem: Extended Abstract" in Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), May 2018.
[ PDF ]

Wen Wang, Jakub Szefer, and Ruben Niederhagen, "FPGA-based Post-Quantum Secure Niederreiter Cryptosystem Demonstration" at the International Symposium on Hardware Oriented Security and Trust (HOST), May 2018.
[ PDF ]

Wen Wang, Jakub Szefer, and Ruben Niederhagen, "FPGA-based Niederreiter Cryptosystem using Binary Goppa Codes", in Proceedings of International Conference on Post-Quantum Cryptography (PQCrypto), April 2018.
[ PDF ] [ BibTeX ] [ CODE ]

Wen Wang, Jakub Szefer, and Ruben Niederhagen, "FPGA-based Key Generator for the Niederreiter Cryptosystem using Binary Goppa Codes" in Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES), September 2017.
[ PDF ] [ BibTeX ]  [ CODE ]

Wen Wang, Jakub Szefer, and Ruben Niederhagen, "Solving Large Systems of Linear Equations over GF(2) on FPGAs" in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), November 2016.
[ PDF ] [ BibTeX ] [ CODE ]

Magnetic Side and Covert Channels

This project investigates how to (ab)use modern smartphones to create side- and covert-channels for communication and to gain understanding of the threats they pose. The project especially looks at magnetic sensors found in commodity smartphones. These sensors require no privileged access nor consent from users and can be potentially abused by malicious apps.

Recent publications:

Nikolay Matyunin, Jakub Szefer, Sebastian Biedermann, and Stefan Katzenbeisser, "Covert Channels Using Mobile Device’s Magnetic Field Sensors" in Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC), January 2016.
[ PDF ] [ BibTeX ]

Sebastian Biedermann, Stefan Katzenbeisser and Jakub Szefer, "Hard Drive Side-Channel Attacks using Smartphone Magnetic Field Sensors" in Proceedings of Financial Cryptography and Data Security (FC), January 2015.
[ PDF ] [ BibTeX ]


Support

NSF Logo We would like to acknowledge Amazon Web Services for the donation of cloud research credits. (2019)

NSF Logo We would like to acknowledge the National Science Foundation for the grants supporting our research. (2014 ~ Present)

Altera Logo We would like to acknowledge FPGA board donations from the Altera University Program (now part of Intel). (2014, 2015, 2018)

Verisign Logo We would like to acknowledge a monetary gift from Verisign. (2014)

Xilinx Logo We would like to acknowledge FPGA board donations from the Xilinx University Program. (2013, 2017)