Research Projects

Hardware Verification

This project investigates developing a new hardware security verification methodology that hardware processor architects can deploy to check security properties of their architectures in a scalable and semi-automated manner at design time. The project combines hardware description tools and languages with model checkers and theorem provers to create the methodology.

Recent publications:

Shuwen Deng, Doğuhan Gümüşoğlu, Wenjie Xiong, Y. Serhan Gener, Onur Demir, and Jakub Szefer, "SecChisel: Language and Tool for Practical and Scalable Security Verification of Security-Aware Hardware Architectures", February 2017.
[ ePrint ]

Onur Demir, Wenjie Xiong, Faisal Zaghloul, and Jakub Szefer, "Survey of Approaches for Security Verification of Hardware/Software Systems", August 2016.
[ ePrint ]

Physically Unclonable Functions

This project explores the design and implementation of novel Physically Unclonable Functions (PUFs). A PUF is a piece of hardware that has unique and stable physical characteristics, which emerges due to variations in the fabrication processes. The project focuses on leveraging the decay characteristics of modern DRAM chips in commodity off-the-shelf systems to design practical DRAM PUFs.

Recent publications:

André Schaller, Wenjie Xiong, Muhammad Umair Saleem, Nikolaos A. Anagnostopoulos, Stefan Katzenbeisser, and Jakub Szefer "Intrinsic Rowhammer PUFs: Leveraging the Rowhammer Effect for Improved Security" in Proceedings of the International Symposium on Hardware Oriented Security and Trust (HOST), May 2017.
[ PDF ] [ BibTeX ] [ CODE ]

Wenjie Xiong, André Schaller, Nikolaos A. Anagnostopoulos, Muhammad Umair Saleem, Sebastian Gabmeyer, Stefan Katzenbeisser, and Jakub Szefer, "Run-time Accessible DRAM PUFs in Commodity Devices" in Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES), August 2016.
[ PDF ] [ BibTeX ] [ CODE ]


Post-Quantum Cryptography

This project explores implementing new types of cryptographic algorithms and optimizing their area, performance and energy needs, as well as integrating them as accelerators into real cloud servers. Current focus of the project is on code-based cryptographic algorithms which are expected to be secure even against attacks that leverage quantum computers.

Recent publications:

Wen Wang, Jakub Szefer, and Ruben Niederhagen, FPGA-based Key Generator for the Niederreiter Cryptosystem using Binary Goppa Codes" in Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES), September 2017.

Wen Wang, Jakub Szefer, and Ruben Niederhagen, "Solving Large Systems of Linear Equations over GF(2) on FPGAs" in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), November 2016.
[ PDF ] [ BibTeX ] [ CODE ]

Magnetic Side- and Covert-Channels

This project investigates how to (ab)use modern smartphones to create side- and covert-channels for communication and to gain understanding of the threats they pose. The project especially looks at magnetic sensors found in commodity smartphones. These sensors require no privileged access nor consent from users and can be potentially abused by malicious apps.

Recent publications:

Nikolay Matyunin, Jakub Szefer, Sebastian Biedermann, and Stefan Katzenbeisser, "Covert Channels Using Mobile Device’s Magnetic Field Sensors" in Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC), January 2016.
[ PDF ] [ BibTeX ]

Sebastian Biedermann, Stefan Katzenbeisser and Jakub Szefer, "Hard Drive Side-Channel Attacks using Smartphone Magnetic Field Sensors" in Proceedings of Financial Cryptography and Data Security (FC), January 2015.
[ PDF ] [ BibTeX ]


Split Virtual Machine Execution

This project explores an innovative idea of Split-VM execution, a new technique that will allow for a VM to be broken up into smaller pieces and to continue executing as one, while the pieces are on different physical servers.

Recent publications:

Junaid Nomani and Jakub Szefer, “Predicting Program Phases and Defending Against Side-Channel Attacks using Hardware Performance Counters” in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), June 2015.
[ PDF ] [ BibTeX ]


Support

NSF Logo We would like to acknowledge the National Science Foundation for the grants supporting our research. (2014 ~ Present)

Altera Logo We would like to acknowledge FPGA board donations from the Altera University Program. (2014, 2015)

Verisign Logo We would like to acknowledge a monetary gift from Verisign. (2014)

Xilinx Logo We would like to acknowledge FPGA board donations from the Xilinx University Program. (2013)